1. Technical Field
The present invention relates to a semiconductor device, particularly to the ones in which bulk structures and silicon-on-insulator (hereafter “SOI”) structures are combined on the same substrate.
2. Related Art
Field-effect transistors formed on SOI substrates have been attracting attention, due to their high level of usability such as easiness in device isolation, latch-up free characteristics, and a small source/drain junction capacitance. Particularly, researches for achieving the operation of the SOI transistors in a fully depleted mode have been very active, since fully depleted SOI transistors allow rapid operations with low-power consumption, and can be driven with low-voltage. A method of forming the SOI transistors at a low cost, by forming SOI layers on bulk substrates, is disclosed as an example of related art. In the method disclosed in the example of related art, Si/SiGe layer is deposited on an Si substrate, and thereafter, a hollow portion is formed between the Si substrate and the Si layer, by selectively removing only the SiGe layer, using the difference in etching rate between Si and SiGe. Subsequently, by performing thermo oxidation of Si that is exposed inside the hollow portion, SiO2 layer is buried between the Si substrate and the Si layer, thereby forming a BOX layer between the Si substrate and the Si layer.
T. Sakai et al. “Separation by BondingSi Islans (SBSI) for LSI Application”, Second International SiGe Technology and Device Meeting, Metting Abstract, pp. 230-231, May 2004, is the above-referenced example of related art.
However, in the case of combining the bulk structure and the SOI structure on the same substrate, an interference caused by the substrate noise may occur between the circuit blocks, depending on the arrangement thereof, resulting in a problem that the reliability declines in the semiconductor device. On the other hand, if the sufficient distance is provided between the adjacent circuit blocks, so as to reduce the interference caused by the noise between the circuit blocks, then the chip size increases, resulting in a problem of causing an increase in packaging area and cost.